Endeavor Intertech
Introduces Unified Simulation™,
a System-on-Chip Multi-core
System-Level
Integrated Simulation
Environment (ISE)
The
ISE Consists of Highly Integrated Models at Varied Abstraction Levels Working
Together to Address Multi-core Co-Design and Verification Bottlenecks
HILLSBORO, Oregon, June 15, 2001—Endeavor
Intertech Corporation today announced the availability of Unified Simulation
technology. The Unified Simulation ISE
provides the system engineer with uncommon control over both hardware and
software design and verification. The
hardware or software engineer can dynamically choose simulation model
components needed to support their efforts, whether that be comparing
system-level hardware design tradeoffs, verification of SoC hardware,
pre-silicon middleware development, or final application testing—complete with
RTOS support—prior to silicon availability. Endeavor will be demonstrating the benefits of Unified Simulation at the
Design Automation Conference June 18-20, 2001 in booth #340.
The growing complexity of SoC designs has
exacerbated the issues associated with verifying the hardware and/or software
involved in these systems. RTL
simulation has had a significant impact in this area, but is being stretched
beyond its limit by demands for higher speed and interoperability. Hardware/software co-verification has held
out great promise, but the current generation of products has provided
disappointing results due to high costs and low model accuracy.
Unified Simulation was developed to provide SoC
engineers with a fully integrated set of simulation models that can be
dynamically configured to the needs of the engineering task at hand. The flexibility of the Unified Simulation
ISE makes reconfiguring the topology of the models easy, because they are
constructed like fully interchangeable building blocks. There are three primary building blocks in
Unified Simulation; the 50-100 MIPS (million instructions per second) Velociss™
models, the cycle-accurate 400,000 IPS Precyse™ models, and the
co-verification/multi-simulation connectivity tool CoOperate™.
Each of these models can be connected and
synchronized with simulators representing other architectures, as well as HDL
simulators for cycle-accurate co-verification. Thus, the software developer can take advantage of the higher
performance model to develop and test complete applications—connecting to
co-verification if and when necessary—well before the silicon is
available. Hardware designers, on the
other hand, may choose to access multiple cycle-accurate models, fully
synchronized, and integrate them with an HDL simulator to verify the
functionality of a device written in HDL under a load similar to the final
design.
“Unified Simulation modules are controlled by a simple configuration tool that can be
modified to dynamically alter the simulation topology required by the
developer,” offered Dan Budge, vice president of Endeavor Intertech. “The ISE is integrated under a single user
interface, typically the embedded processor’s integrated development
environment or debugger interface. So
not only is Unified Simulation surprisingly flexible and easy to configure,
there is virtually no additional learning curve.”
Unified Simulation components are used within other vendor’s EDA tool environments as well,
including co-verification, co-design, and verification products by Synopsys,
Mentor Graphics, Cadence, Innoveda, and others.
Endeavor works with processor core designers to target Unified Simulation technology for DSP,
RISC and other architectures. A
targeted Unified Simulation package for the DSP Group PalmDSPCore®
is scheduled to be available next month. Targeted Unified Simulation ISE packages are priced at under $40,000 in
the United States, and include the three primary modeling components for the
target plus the ISE dynamic configuration tools.
About Endeavor Intertech Corporation
Endeavor Intertech specializes in
Unified Simulation, an Integrated Simulation Environment (ISE) consisting of
high performance processor models, co-verification interfaces and tools for
hardware and software verification. Endeavor Intertech has been in the business of developing EDA tools and
models since 1997, and continues to establish itself as an innovative leading
solution provider for EDA and processor core design customers.
Endeavor creates models for DSP,
VLIW, RISC, and other embedded cores and processors. For
more information on Endeavor Intertech’s Unified Simulation ISE and its underlying
component products Precyse, CoOperate, and Velociss, as well as other
hardware/software simulation tools, please contact your Endeavor Intertech
representative at info@endeav.com, or
1-503-628-6200 x100. Additional
information is available on the web at http://www.endeav.com
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Unified Simulation,
Precyse, Velociss and CoOperate are trademarks of Endeavor Intertech
Corporation.
DSP Group and PalmDSPCore are registered or non-registered trademarks of DSP Group, Inc.
Other brands and products referenced herein are the
trademarks or registered trademarks of their respective holders.
