New Processor Core
Model Shortens System Verification Time
for IBM PowerPC 440™
Simulation
Model Integrates with EDA Tools for SoC Verification Solution
HILLSBORO,
Oregon, December 11, 2001 –Endeavor Intertech Corporation announced
today the release of its TransAccurate™ bus-accurate, multi-core
System-on-Chip (SoC) processor model of IBM’s PowerPC 440 core
architecture.
This model can be used to interchange with the IBM
PowerPC 440 RTL core model, and when linked with Endeavor’s available
PPC440 Bus Functional Model (BFM), will enable developers integrating the
core into SoC designs to validate hardware and software interfaces prior to
chip fabrication. The
TransAccurate model can be synchronized with multiple instantiations of
itself for true multi-core simulations of complex designs.
The model is also valuable for starting software development long
before the hardware for a new PPC440 SoC is completed.
This can result in potential design cycle reductions of several
months.
Endeavor’s TransAccurate model processes up to one
million cycles each second. Verification
code that executes in the PowerPC 440 core can now run four to five orders
of magnitude faster than an RTL model.
At the same time, bus transaction accuracy is maintained so that
external peripherals simulated in HDL communicate accurately each bus clock
cycle. PowerPC 440 verification
test suites results can be viewed in hours rather than days or weeks.
Further, the high accuracy of bus transactions insures the results
are trustworthy.
“IBM sees a strong need for fast and accurate SoC
modeling solutions to help preserve the time-to-market advantages of our
cores,” said Ricardo Gariazzo, IBM’s PowerPC Enablement Manager. “Co-verification-ready models can enable our customers to
use system prototypes for verifying the functional performance of their
applications. Shortening
verification cycles allows our customers to focus on other areas that can
provide them real competitive advantages.”
This model expands Endeavor’s comprehensive line of
PowerPC models that are integrated into leading tool environments and design
flows such as the Endeavor CoOperate™ and CoSimple™ co-verification
environments and Innoveda V-CPU, and include PPC405 and PPC440 processor and
bus functional models.
Pricing and Availability
The TransAccurate PPC440 model is fully integrated with
the Gnu GDB debugger. Endeavor’s
TransAccurate PPC440 models are available immediately on Sun workstations
for US$9,999. Linux, AIX and
Windows versions will be available soon.
A complete PowerPC 440 “CoSimple” direct-to-HDL
hardware/software co-verification package is available from Endeavor for
US$12,999. It includes the
TransAccurate ISS, PPC440 BFM, GNU debugger, with interfaces to a VCS or MTI
HDL simulator. CoSimple enables
our customers to simply drop the model into their design and co-simulate.
No additional tools or EDA environments are required.
About Endeavor Intertech Corporation
Endeavor specializes in high performance processor
models, co-simulation interfaces and tools for hardware and software
verification. Endeavor has been
in the business of developing EDA tools and models since 1997, and has
quietly established itself as a leading model developer for its EDA and
processor design customers. Endeavor
creates processor and bus functional models for DSP, VLIW, RISC, and other
embedded cores and processors.
For more information on Endeavor’s processor models
and other hardware/software verification tools, please contact your Endeavor
Intertech representative at info@endeav.com,
or 1-503-628-6200 x100. See
Endeavor Intertech on the web at http://www.endeav.com.
###
TransAccurate PPC440, Precyse,
CoOperate, CoSimple and IPSim are trademarks of Endeavor Intertech
Corporation. PowerPC and
PowerPC 440 are trademarks of IBM. Other
brands and products referenced herein are the trademarks or registered
trademarks of their respective holders.
For more information, contact:
For Endeavor
Intertech Corporation:
David N. Glass
Tel: (503) 628-6200 x100
e-mail: glass@endeav.com |
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