Introduction

Endeavor is a highly experienced engineering firm that concentrates its efforts in simulation development for the System-on-Chip (SoC) market.  Our position in this market is somewhat unique in that we produce simulators—such as Precyse™—that execute over 400,000 instructions per second while maintaining full cycle and pin accuracy.  In addition, these Precyse models are end user extensible, and can be set up to be used in a multi-simulator environment while still maintaining full cycle accuracy.  We have developed multi-simulation capabilities through CoOperate™ to work with not only our own processor models, but with those produced by other parties. Furthermore, CoOperate provides a Co-Verification interface to most popular Verilog and VHDL hardware simulators, without compromising accuracy. 

Project Description

The architectures we work with represent the newest generation of processors in the embedded MPU, DSP, and MCU arena.  They often support higher clock speeds, and multi-stage pipelines that are capable of issuing multiple instruction operations per cycle. In addition, they often have dynamic branch prediction and advanced cache and memory management units, which increase total system performance. 

Unified Simulation consists of three primary components, which together represent a state-of-the-art multi-core, multi-simulation.  To target Unified Simulation to a new processor architecture core, the following development process is put into place:

Unified Simulation™ Components

Precyse cycle-precise model

The Precyse model will support the complete processor core instruction set and all internal registers including all timers.  Precyse will provide cycle accurate support for the internal and external core interfaces.  In addition, external control pins—such as reset, interrupt, and the like—will be supported in a cycle accurate manner.   The model will be user-configurable with respect to any caches and supported configuration pins.  Precyse will be developed to support the debugger of the customer’s choice.

Endeavor will develop this model to be used as a fully functional stand-alone software development tool and in a complete Co-Simulation package.  When used as a standalone tool, Endeavor will provide user configurable memory components that can be connected to the processor core memory interface.  Of course the end user can “extend” the functionality of Precyse by adding their own components via Endeavor’s IPXtend™ interface.  By using IPXtend, the user can add external devices to their model with a simple to use ‘C’ (or C++) language interface while still maintaining cycle accuracy.   When used as part of a Co-Simulation tool, all supported pins are exported/imported to/from the CoOperate-attached HDL simulator.  This does not preclude the user adding IPXtend model—in fact it is often useful to have some a combination of IPXtend and Co-Simulation components to maximize efficiency. 

Once Endeavor completes coding for an Precyse, extensive testing is performed to insure that the processor is both functionally and clock-cycle accurate. Functional accuracy is assured by successful completion of Functional Accuracy tests provided by the IP core designer.   Cycle accuracy is tested by comparing the output of RTL simulation of the core with the cycle/pin outputs of Precyse while running test programs designed by both the customer and Endeavor.  Upon acceptance of the resulting test vectors, the core manufacturer then confers a “Certified Accurate” label on Precyse.

TransAccurate simulation models

The TransAccurate Simulator will accurately represent all the registers and instructions supported by the core, and will be significantly faster execution than even our fast cycle-accurate model.  TransAccurate simulators will execute at the level of millions of operations per second, often over 2 MIPS on a standard PC.  Additionally, TransAccurate simulators are faster to develop, and therefore can be ready for use in less calendar time than a Precyse cycle-accurate model.

While this simulator will not be cycle accurate for instruction, at the bus transaction level, it is cycle-accurate.  Thus, communication between a hardware simulator and the TransAccurate model will be cycle-accurate where synchronization matters.  This co-simulation link provides the software developer with a path to execute their applications on devices external to the core that are not yet available in silicon.  In this way, the application for the final system-on-chip can be finalized before the chip itself is fabricated.

The TransAccurate model can be integrated to Precyse, allowing the developer to toggle from MIPS performance to high precision mode or back at any code breakpoint. 

CoOperate Co-Simulation Package

CoOperate synchronizes multiple simulation models to the lowest common accuracy level of the simulation models involved, and is capable of maintaining cycle-accurate synchronization amongst models—even if the models represent clocks running at different speeds.   Moreover, each of these models can communicate with one another through CoOperate using the pins and interfaces that have been exposed by the design.  CoOperate’s data communication pipeline has been optimized for performance over network connections as well, allowing such synchronized models to be running on different hosts, and under different operating systems.

Further, CoOperate enables hardware/software co-simulation between each of the software models and the most popular Verilog or VHDL hardware simulators.  For the software developer, this means that they can now develop and test final, unmodified applications prior to silicon availability, moving software development into parallel with the hardware effort, shaving months off of time-to-market.  For the hardware developer, CoOperate makes it possible to verify even the most difficult-to-test hardware components because the actual application software can be used to verify components under final design conditions.

Project Plan

1. The first step we will undertake is to prepare a detailed Functional Specification for the processor core Unified Simulation components.  This specification would detail all features and limitations of the components, user interfaces, and operational characteristics.  A Test Plan would also be produced, which would detail the acceptance test procedures for each Unified Simulation component including description of test circuits, and testing methodologies.

2. Building upon our existing simulation framework and class libraries, we would then begin design of the Unified Simulation models and tools.  Typically after about 2 weeks time, visit the IP designer’s facility, discuss our design with their engineers, and ask any questions regarding internal timing of operations. We realize that this engineering time is an extremely valuable resource and we do not waste their time.  We generally only need a few days of the IP designer’s time given our years of experience developing processor core models.

3. Next, we finish the design and develop the Unified Simulation tools.  We can develop models quickly because of our model development tools and the “off the shelf” code that we have developed over the years.  For Precyse, in order to insure cycle accuracy, we employ a high-speed event driven simulation kernel of our own design.  All of our code is written in C++ where we can make use of a library of simulator base classes that we have developed over the years.  For example, we have base classes for things such as busses, pipelines, loaders, and instructions.  During this code development period, we would require access to technical contacts inside the IP designer’s team to ask technical questions (by email or phone) as they come up.  Typically, these questions may be routed through technical support, then, only if necessary, to a design engineer. This has an additional benefit of “shaking out” the processor core user documentation as the interface manuals and processor manuals are our primary source of information.

4. As completion of the tool suite draws near, we will require a set of assembly language functional tests for the processor core.  These tests will serve as the validation of the functional integrity of the models.  The successful completion of these tests defines the alpha release of the Unified Simulation modeling component.

5. While the Precyse and/or Velociss model is nearing alpha release, Endeavor will begin the design of the CoOperate component.  The coding of this Co-Simulation component would be done in parallel with the cycle accuracy correction/validation on the models.  In the end, the core model will be coupled to CoOperate and final system testing would begin.

6. In order to test the completed CoOperate Co-Simulation system, test circuits (VHDL and Verilog) must be constructed.  These test circuits then become part of the “CoOperate Support Package” that is delivered to the end user.  In addition automated test and installation scripts are constructed to facilitate regressions and to complete the end user deliverables.  This constitutes the first shippable release.

7. Endeavor will provide on-going maintenance and support, internally and for IP customers if desired, for all Unified Simulation components developed under this arrangement.