Unified Simulation Accelerates Pre-silicon Software Development

 

Unified Simulation enables software development to begin in parallel with hardware development.  Software developers no longer need to wait for silicon because of the accuracy and connectivity of Unified Simulation's underlying components.

For example, TransAccurate models accurately simulate the instructions of an architecture, while simulating execution of those instructions at MIPS speeds.  Thus, significant portions of complex software applications can be developed and tested using the target processor's embedded tools, with full debug access, on an existing Windows PC, Linux PC, or Sun Workstation.

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But what happens when the software developer needs to access a hardware device that is not in the core?  Does software development grind to a halt?

No, because both TransAccurate and Precyse models can synchronize with VHDL and Verilog representations of the external hardware device, using CoOperate.  Thus, software developers can test their full applications, without stubs in the code, with the latest pre-silicon designs the hardware team is verifying.  

Further, it does not matter whether they are working on middleware drivers or application layers, because CoOperate synchronizes with the same accuracy of the model.  Therefore, if a Precyse cycle-accurate model is being used to test a driver that needs to know exactly when a value or an interrupt is received from the device, CoOperate coordinates the bus interactions of the Precyse model and the Hardware Description Language (HDL) simulated device on a cycle-for-cycle basis.  On the other hand, CoOperate automatically matches the instruction-accurate model to the HDL at the instruction level.

With Unified Simulation, software development, integration, and testing can be completed before silicon availability, significantly reducing overall time to market.  Even better, Unified Simulation is priced sensitive to software development budgets, making your project, and Endeavor Intertech tools a win/win proposition. 


Unified Simulation Modeling Components

Precyse:

cycle-accurate multi-core simulation models

Velociss

embedded core models with native host simulation performance

CoOperate:

multi-simulation/ co-verification synchronization and control

SystemC Support

Native SystemC models

SystemC interfacing with other HDL models

 

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