| System-on-a-Chip (SoC) oriented hardware design and
development can involve using hardware/software
Co-verification simulation techniques. Co-verification integrates
various models of processor cores and other IP together in a single
simulation to verify the accuracy of the resulting design. The
accuracy of each of the components in a Co-verification environment
are crucial to having a high confidence in the final design.
Bus models are an essential part of a co-verification
environment. A bus model is the primary interface
between a software Instruction Set Simulator (ISS) and the VHDL or
Verilog hardware simulator. They allow the hardware
simulator to synchronize with and pass data to and from the software
simulator.
Endeavor Intertech, in addition to developing high performance,
high accuracy ISS models, also develops bus models on a custom basis
for our customers. These bus models are designed specifically
to interact with the ISS on one side, and your EDA vendor's hardware
tools on the other. Endeavor can develop a custom bus
model for you even if you are using an ISS developed elsewhere.
Endeavor's custom bus models are traditionally developed in HDL,
and fully tested and integrated into your unique co-verification
environment. Endeavor has extensive skill working with most major EDA tool vendors,
including developing Bus Functional Models (BFM) for
the Innoveda V-CPU and Synopsys' Eaglei environments, and Bus Interface Models (BIM) for
the Mentor Graphics Seamless environment. Our engineering
staff has the experience to get you up and running quickly in any co-verification
system and to avoid the pitfalls associated with
developing such models.
We would be happy to discuss your
co-verification simulation needs further. Please contact
us. |
