The first co-simulating model available for advanced FPGAs

CoSimple, the latest of Endeavor’s Unified Simulation™ product line, contains Endeavor’s TransAccurate™ instruction set simulator, rich interactive debugging capabilities based on the GNU gdb interface, and a cycle-accurate Virtual Bus Model.  CoSimple boasts flexible synchronization and communication with hardware simulators like Model Technology’s ModelSim Verilog and VHDL products.  For under $10,000 in single quantities, CoSimple provides virtually the same co-verification capabilities of existing co-verification environments, in a simple-to-use package.  

Under the surface, CoSimple is not only simulating instructions for the debugger, but also providing the inter-process communication and synchronization between the software debugger and the hardware debugging environment.  Thus, hardware developers can run test vectors, break on a specific instruction, and compare resultant waveforms. 

Virtex-II Pro