As the complexity of SoC designs increase, multiple processor cores are being integrated into a single chip in an effort to provide maximum compute power while minimizing design and test cycles.  However, verifying both hardware accuracy as well as software reliability on these mammoth systems can be a problem, because up to now, tools from various vendors did not work together.  Endeavor’s Unified Simulation solves this problem by integrating simulation model components like Precyse and TransAccurate, as well as ISS models from multiple vendors into a synchronized system simulation that provides a high throughput communication pipeline between the models. 

Unified Simulation’s advanced multicore support enables software developers to debug applications split across two or more cores as easily as starting another debugger process. They can focus on one core by single-stepping its application while all other debuggers run—and they remain synchronized in relation to each other.

Unified Simulation takes care of all the interactions necessary — both from the clock’s standpoint and from the debugger processes. Further, Unified Simulation’s innovative methodology accurately handles cores with multiple clock domains without special glue logic. 

For example, Unified Simulation's CoOperate component synchronizes multiple simulation models to the lowest common accuracy level of the simulation models involved, and is capable of maintaining cycle-accurate synchronization amongst models — even if the models represent clocks running at different speeds.   Moreover, each of these models can communicate with one another through CoOperate using the pins and interfaces that have been exposed by the design.  CoOperate’s data communication pipeline has been optimized for performance over network connections as well, allowing such synchronized models to be running on different hosts, and under different operating systems.

Further, CoOperate enables hardware/software co-simulation between each of the software models and the most popular Verilog or VHDL hardware simulators.  For the software developer, this means that they can now develop and test final, unmodified applications prior to silicon availability, moving software development into parallel with the hardware effort, shaving months off of time-to-market.  For the hardware developer, CoOperate makes it possible to verify even the most difficult-to-test hardware components because the actual application software can be used to verify components under final design conditions.