Hardware verification can be a tough job, especially in SoC designs in which there are hardware components that are almost impossible to test without the entire system in place. This is why we designed Unified Simulation with the ability to interact as it does. You can configure your final, unmodified application—including RTOS—to perform high speed simulation, right up to a predefined breakpoint in the code.

At the breakpoint, you can advance into full cycle-accurate mode, with synchronized access to the hardware simulation model of the component(s) you need to verify. With the software debugger controlling the application, and the HDL simulator in cycle-lock step, we make the successful verification of even the most difficult components possible.