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Targeted
TransAccurate Models
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TransAccurate models are functionally accurate relative to the processor
core, and cycle-accurate for all bus transactions.
This technology is a nice compromise between full cycle-accuracy,
which requires a larger investment per model and offers lower
performance; and a model that is only functionally accurate, not
offering enough precision to make a co-simulation session terribly
meaningful. TransAccurate
models can be developed quickly, have MIPS-speed performance, and
provide the cycle-for-cycle synchronization with an HDL simulator
through our CoOperate or CoSimple co-simulation interfaces.
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| TransAccurate
Features |
| 1-2 MIPS
simulation speeds |
| Uses existing
development tools |
| Full debug
capability, including access to registers, memory, and
breakpoints |
| Integrates with
CoOperate and CoSimple for application-oriented co-simulation |
| Bus transactions
are cycle-accurate for accurate co-simulation |
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